By Bang-Sup Song (auth.), Arthur H. M. Roermund, Herman Casier, Michiel Steyaert (eds.)
Analog Circuit Design comprises the contribution of 18 tutorials of the 18th workshop on Advances in Analog Circuit layout. every one half discusses a selected to-date subject on new and necessary layout principles within the region of analog circuit layout. each one half is gifted through six specialists in that box and state-of-the-art details is shared and overviewed. This e-book is quantity 18 during this winning sequence of Analog Circuit layout, delivering beneficial info and perfect overviews of
- shrewdpermanent info Converters,
chaired by means of Prof. Arthur van Roermund, Eindhoven collage of expertise
- Filters on Chip,
chaired via Herman Casier, AMI Semiconductor Fellow
- Multimode Transmitters,
chaired by way of Prof. Michiel Steyaert, Catholic college Leuven
Analog Circuit layout is an important reference resource for analog circuit designers and researchers wishing to maintain abreast with the most recent improvement within the box. the educational assurance additionally makes it appropriate to be used in a sophisticated layout course.
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Extra info for Analog Circuit Design: Smart Data Converters, Filters on Chip, Multimode Transmitters
It has been found empirically that the optimal value for the correction parameter b1 is different from sample to sample, whereas for b3 it is constant. Therefore only b1 is iteratively updated by the digital error estimation block, reducing the design complexity of the digital calibration algorithm. More details on the digital background error estimation can be found in  (Fig. 6). 3 High-Resolution and Wide-Bandwidth CMOS Pipeline AD Converters digital post-processing stage 1 Vin SH + – Vres back- Dres end Dres,corr correction bk ADSC 53 DAC error estimation D1 e n c o d e r Dout mode Fig.
2 Digital Calibration of Non-Linearity Digital calibration is an attractive solution to overcome linearity limitations, while taking advantage of the high density and low power consumption of digital circuits in nm-CMOS. The additional design complexity and the extra power consumption of digital calibration circuits should be justified by significant power savings in the analog circuits of the ADC. In an ADC non-linearity may result from various sources of errors. These errors can be either static or dynamic.
For a GSM system, the difference in channel attenuation for near and far H. M. van Roermund et al. V. 2010 43 44 H. Van de Vel channelizer ch. 1 ch. 2 ADC ch. n LNA LO individual channels multiple channels ADC input 1 3 n 4 2 0 fs /2 input frequency Fig. 1 Typical multi-channel receiver users demands an even higher SFDR of 100 dB. The ADC’s resolution should then be 14 b or higher such that the errors and spurs arising due to the quantization are at least 10 dB lower than the required maximum level.
Analog Circuit Design: Smart Data Converters, Filters on Chip, Multimode Transmitters by Bang-Sup Song (auth.), Arthur H. M. Roermund, Herman Casier, Michiel Steyaert (eds.)